Lenophis wrote:I think the problem, at least partially, is that it appears both C3/0F75 and C3/A991 are setting up DMA with the same channel. When DMA is to happen, a series of routines starting at C3/1463 executes. In this case, C3/14AC executes.
looking at Bank C3, it seems that only DMA Channel 0 is ever used, of the normal channels. (Is HDMA Channel N separate from DMA Channel N, or can they not both be active at once?)
maybe we could make C3/0F75 use new DMA setup variables, and have C3/1463 call a new DMA routine that uses Channel 1+. now, we might also have to mimic every place that zeroes $1B to prevent C3/14AC from executing, and adapt it to our new variable and function.
adapting C3/9E23 and/or C3/9E37 to use a new DMA channel could be trickier, as unlike C3/0F75, they're called from multiple places.
i noticed that some calls to C3/9E23 were neighbored by calls/branches to $1368 to trigger NMI. so i took inspiration, and changed the "JSR $0F75" to immediately call C3/1368 afterwards. sure enough, the MP cost is updating immediately after button presses. however, spell descriptions print out noticably slower, repeat L/R scrolling is slowed down, and repeat arrow scrolling is slowed down with display glitches.
a compromise might be to issue the NMI only in a wake of a keypress. with a free RAM variable, i should be able to do this with the Y and L/R buttons, as i know how C3/27E2 detects them. how it detects arrow presses eludes me, and issuing an NMI after each arrow "repeat" might not avoid the aforementioned glitchy slowness (it depends how many repeats per second there are).
another compromise is to not do the entire NMI after C3/0F75, but just the DMA transfer. that should be faster... do we have to wait for H-Blank, V-Blank, or what else?
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EDIT: okay, i tried a version that after calling C3/0F75, waits for V-Blank, then calls C3/14AC for the DMA transfer. it still seems to fix the bug, and has far less slowdown. though there is still some slowdown when repeat arrow scrolling, albeit with no display glitchiness.
i'm hoping that this DMA transfer isn't being done too nearly before or after the usual one reached via C3/1460, and that both have time to complete.